Full-Stack Simulation Framework for Cryogenic, Superconductor, and Fault-Tolerant Quantum Computing

 High-performance computing and data center industry always requires the fastest and most power-efficient computer systems. However, facing the end of single-thread and multi-thread performance scaling, computer architects now suffer from critical challenges to further improve the performance and power efficiency with conventional room-temperature computing.

To resolve the problems, researchers at Seoul National University, Kyushu University, and Nagoya University have focused on cryogenic/superconducting computing which architects and operates computers at extremely low temperatures. Our research goal is to maximize the performance of conventional computers (i.e., cryogenic/superconducting computing) and to realize the next-generation innovative computers (e.g., superconducting AI accelerator, scalable quantum computer). Our key achievements can be briefly summarized as (1) 77K CMOS-based cryogenic computing, (2) 4K superconductor-based computing, and (3) mK qubit-based quantum computing.

To realize the research, we developed a series of software tools to model the performance and power consumption of various cryogenic/superconducting computer devices and systems (e.g., 77K core, cache, DRAM, cache, network-on-chip, quantum-control processor).

In this tutorial, we plan to introduce our modeling and design tools which can be used for developing (1) cryogenic CMOS-based computer, (2) superconductor-based computer, and (3) fault-tolerant quantum computer. The tutorial is presented as three main sessions as below.

CryoModel: Cryogenic CMOS computer modeling tools
Cryogenic computing, which runs CMOS devices at extremely low temperatures is highly promising thanks to its significant reduction of wire resistance as well as leakage current.

In this session, we will introduce our modeling tools to accurately predict the performance and power consumption of various cryogenic CMOS computer devices. We will cover the modeling methodology, detailed tool usage, and use cases of our cryogenic DRAM, cache, and processor modeling tools. We will also present our cryogenic-optimized architectures which appeared in ISCA 2019, ASPLOS 2020, ISCA 2020, Top Picks 2021, ISCA 2021, and ASPLOS 2022.

Superconductor-based computer design and modeling tools
Superconductor single-flux quantum (SFQ) device operating at 4K or below enables at 4K, enables high-speed and low-power digital logical circuits. To exploit the SFQ device's full potential, we need to develop new architecture and circuit designs to exploit the new device characteristics (e.g., gate-level latching, limited fan-outs, and strict timing window).

In this session, we will introduce SFQ device, its features, our SFQ circuit/microprocessor designs, and area/power modeling which appeared in ISSCC 2019, VLSI 2020, MICRO 2020, Top Picks 2021, and ISCAS 2022.

XQsim: Fault-tolerant quantum control processor modeling tools
10+K qubit fault-tolerant quantum computer is essential to achieve a true sense of quantum supremacy. With the recent effort toward the large-scale quantum computer, architects have revealed various scalability issues in a quantum control processor. But, it has been difficult to identify and resolve the processor's scalability bottleneck due to the absence of a reliable tool. To resolve the challenge, we developed XQsim, an open-source cross-technology quantum control processor simulator.

In this session, we will introduce XQsim's detailed usage and capability based on our real use-case experiences. This session will explain our tools while covering microarchitecture, temperature, and technology exploration which appeared in ISCA 2022.

Agenda

• 09:30 – 10:00am | Welcome: Introduction to cryogenic, superconductor, and quantum computing[Slides]
  • Jangwoo Kim
• 10:00 – 11:00am | CryoModel: Cryogenic CMOS computer modeling tools[Slides][Github]
  • Dongmoon Min, Junpyo Kim
• 11:00 – 12:00pm | Superconductor-based computer design and modeling tools[Slides]
  • Koji Inoue, Masamitsu Tanaka, Teruo Tanimoto
• 12:00 – 01:00pm | XQsim: Fault-tolerant quantum control processor modeling tools[Slides]
  • Ilkwon Byun, Junpyo Kim

Note
Please bring your laptop and install pre-required packages to fully enjoy our tool demonstrations!

• Pre-required packages
  • sudo apt install python3.8-dev python3-pip libprotobuf-dev protobuf-compiler libboost-all-dev
  • python3.8 -m pip install protobuf cython numpy

Organizers & Speakers

• Jangwoo Kim(SNU)
  
• Koji Inoue(Kyushu University)
  
• Masamitsu Tanaka(Nagoya University)
  
• Teruo Tanimoto(Kyushu University)
  
• Dongmoon Min(SNU)
  
• Ilkwon Byun(SNU)
  
• Junpyo Kim(SNU)
  

Related Publications

1. I. Byun, J. Kim, D. Min, I. Nagaoka, K. Fukumitsu, I. Ishikawa, T. Tanimoto, M. Tanaka, K. Inoue, and J. Kim, "XQsim: modeling cross-technology control processors for 10+ K qubit quantum computers." in Proceedings of the 49th Annual International Symposium on Computer Architecture (ISCA'22).
   
2. I. Ishikawa, K. Ishida, M. Tanaka, I. Nagaoka, S. Kawakami, T. Tanimoto, A. Fujimaki, and K. Inoue, "Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device," 2022 IEEE International Symposium on Circuits & Systems (ISCAS'22).
   
3. D. Min, Y. Chung, I. Byun, J. Kim, and J. Kim, "CryoWire: wire-driven microarchitecture designs for cryogenic computing," in Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'22).
   
4. G. Lee, S. Na, I. Byun, D. Min, and J. Kim, “CryoGuard: A near refresh-free robust DRAM design for cryogenic computing,” in Proceedings of the 48th International Symposium on Computer Architecture (ISCA’21).
   
5. I. Byun, D. Min, G. Lee, S. Na, and J. Kim, "A Next-Generation Cryogenic Processor Architecture," 2021 IEEE Micro (Top Picks'21).
   
6. K. Ishida, I. Byun, I. Nagaoka, K. Fukumitsu, M. Tanaka, S. Kawakami, T. Tanimoto, T. Ono, J. Kim, and K. Inoue, "Superconductor Computing for Neural Networks," 2021 IEEE Micro (Top Picks'21).
   
7. K. Ishida, I. Byun, I. Nagaoka, K. Fukumitsu, M. Tanaka, S. Kawakami, T. Tanimoto, T. Ono, J. Kim, and K. Inoue, "SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices," in Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'20).
   
8. K. Ishida, M. Tanaka, I. Nagaoka, T. Ono, S. Kawakami, T. Tanimoto, A. Fujimaki, and K. Inoue, "32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic," 2020 IEEE Symposium on VLSI Circuits (VLSI'20)
   
9. I. Byun, D. Min, G. Lee, S. Na, and J. Kim, "CryoCore: A Fast and Dense Processor Architecture for Cryogenic Computing," in Proceedings of the 47th International Symposium on Computer Architecture (ISCA'20).
   
10. D. Min, I. Byun, G. Lee, S. Na, and J. Kim, "CryoCache: A Fast, Large, and Cost-Effective Cache Architecture for Cryogenic Computing," in Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'20).
    
11. I. Nagaoka, M. Tanaka, K. Inoue, A. Fujimaki, “29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic," 2019 IEEE International Solid State Circuits Conference (ISSCC'19).
    
12. G. Lee, D. Min, I. Byun, and J. Kim, “Cryogenic computer architecture modeling with memory-side case studies,” in Proceedings of the 46th International Symposium on Computer Architecture (ISCA'19).